Different types of memories are used depending on the intended applications and desired performances.
Thus, SRAM type memories, or static random access memories offer extremely fast write times, which are needed for calculations by a microprocessor, for example. The major disadvantage of these memories is that they are volatile, and the relatively large size of the memory point means that it is not possible to get a great deal of storage capacity in a reasonable volume.
DRAM type memories, or dynamic random access memories are capable of storing electrical charges in capacities, and offer a large storage capacity. However, the writing times for these memories are slower (several tens of nanoseconds) than for the SRAM type memories and they too are volatile, the information retention time for these memories being in the order of a few tens of milliseconds.
For applications that need the information to be stored even in the event of a power failure, EEPROM or FLASH type non-volatile memories which store electrical charges on the floating gates of field effect transistors are used. However, these memories have drawbacks:                long writing times (several microseconds),        limited density because the reduction in size of transistors causes a reduction in the read signal, that is to say the difference between the two states of the memory point, and a shorter information retention period,        limited number of write cycles because the information retention capacity is reduced together with the write cycles due to the creation of errors in the transistor gate oxide, which enables electrons to escape from the floating gate.        
More recently, other types of rewritable non-volatile memories have appeared, based on active materials such as ionic conduction materials (Conductive Bridging RAM (CBRAM) memories), metal oxides (Oxide Resistive RAM (OxRAM) memories), ferroelectric materials (Ferroelectric RAM (FERAM) memories), magnetic materials (Magnetic RAM (MRAM) memories), spin magnetic transfer materials (Spin Torque Transfer RAM (STTRAM) memories), or even phase changing materials (Phase Change RAM (PCRAM) memories). These are all resistive type memories, that is to say they may have at least two states, “OFF” or “ON” corresponding to the transition from a resistive state (“OFF” state) to a less resistive state (“ON” state).
The benefit resistive memories have is that they can be integrated into extremely dense arrays using crossbar type integration (also referred to as “crosspoint” integration):
Such an architecture 100 is shown in FIG. 1 and comprises a plurality of access lines 101 and 102 and a plurality of non-volatile, rewritable type memory cells 103 based on active materials (CBRAM cells for example). The access lines are formed by parallel upper bitlines 101 and lower wordlines 102 perpendicular to the bitlines, elementary cells 103 being sandwiched at the intersections between the bitlines 101 and the wordlines 102. Architecture 100 thus forms a grid in which each memory cell 103 may be addressed individually by selecting the appropriate bitline and wordline.
However, this architecture is associated with certain problems.
For example, the read phase of a cell state is performed by polarisation of the desired row and column; it is then possible to observe a parasitic leakage current passing through the adjacent cells. This phenomenon is illustrated in FIG. 2.
FIG. 2 shows an addressing architecture 200 of a plurality of memory cells (in this case four cells C11, C21, C22 and C12) of the non-volatile, rewritable type and based on active materials (CBRAM cells for example). This matrix 200 comprises two bitlines 201 and 202 and two wordlines 203 and 204 which particularly enable the resistive state of each cell C11, C21, C22 and C12 to be read. In the present case, we will here assume that:                cell C11 is in the OFF state (strongly resistive state);        cell C21 is in the ON state (weakly resistive state);        cell C22 is in the ON state (weakly resistive state);        cell C12 is in the ON state (weakly resistive state).        
In order to read the resistive state of cell C11, wordline 201 and wordline 204 have to be polarised respectively (by applying a potential difference Vbias between these two wordlines).
In theory, the measuring current should only travel in the direction shown by dotted arrow 205.
In practice, because the other three cells are in the ON state, a parasitic leakage current, represented by arrow 206, passes through non-resistive cells C21, C22 and C12. Particularly in the unfavourable situation in which the elements adjacent to the cell to be measured are in the ON state, this leakage current may interfere with the measurement to the point of rendering it impossible to distinguish between the ON and OFF states in the cell to be measured. Thus, FIG. 3 shows a chart indicating the resistance values of the cells C11, C21, C22 and C12. In the present case, a resistance value equal to 7.9 kΩ will be noted for cell C11, similar to the resistance values of the other three cells, whereas in fact the cell is in the OFF state and therefore has a resistance in the order of MΩ: the measurement is thus completely distorted.
One known solution to this problem consists in adding a p-n junction series diode 207 with each of these cells. Such an architecture is shown in FIG. 4. Identical elements in the figures have the same reference numbers in FIGS. 2 and 4, assuming that cells C11, C21, C22 and C12 in FIG. 4 are in the same resistive states as cells C11, C21, C22 and C12 in FIG. 2.
In this case, since diodes 105 are unipolar, they block the passage of the parasitic current, and thus only allow the current represented by arrow 210, which is induced by the polarisation of bitline 201 and wordline 204 (application of a potential difference Vbias between these two lines).
Accordingly, FIG. 5 shows a chart indicating the resistance values of the individual cells C11, C21, C22 and C12. In the case of the architecture of FIG. 4, this shows resistance values that are consistent with reality, with cell C11 having a resistance equal to 4.2 MΩ (being OFF) compared with the resistance values of the other three cells, which are in the order of a few tens of kΩ: this measurement is therefore correct.
However, the architecture as it is shown in FIG. 4 also presents certain problems particularly with regard to the fact that the diodes have current densities that are still limited in passing mode.
Accordingly, for a given silicon surface it is not currently possible to create a diode having the same surface as the memory cell as well as an adequate passing current Ion (current density of the diodes too low) and a relatively low leakage current Ioff at the same time. This situation presents serious difficulties particularly when a series diode is used with a phase changing type cell PCRAM, which requires large switching currents.
One known solution to this problem consists in using low temperature diodes, which have moderately satisfactory average characteristics in terms of current density (105 to 108 A/cm3). However, the use of these low temperature diodes presents a serious problem for multilayer crossbar integrations (several layers of series diodes with superposed resistive memory cells in order to increase integration density; in other words, several architectures 300 such as those shown in FIG. 4 are superposed). In fact, in order to manufacture a low temperature diode an activation annealing process must be carried out at high temperature (typically 1100° C.). Such annealing temperatures are not compatible with resistive memories on a chalcogenide base (PCRAM and CBRAM), which do not respond well to manufacturing temperatures in excess of 450° C.
An alternative to using series diodes with the memory cell consists in using an architecture 400 (see FIG. 6) that comprises a series electrolytic cell 401 having a resistive cell memory 402, the two cells being located between a bitline 403 and a wordline 404; an example of such a configuration is described in the document U.S. Pat. No. 7,382,647. The benefit of such a salutation is that it enables relatively high current densities in passing mode.
The function of electrolytic cell 401 is similar to that of a CBRAM type device and it is based on the formation of metallic elements called “dendrites” inside the solid electrolyte between two electrodes when these electrodes are raised to appropriate potentials for each. The formation of these dendrites makes it possible to obtain a given electrical conductivity between the two electrodes. By modifying the potentials applied respectively to each electrode, it is possible to modify the distribution and number of dendrites, and thus also to modify the electrical conductivity between the two electrodes. For example, by inverting the potential between the electrodes it is possible to eliminate or reduce the dendrites, and so to prevent or considerably limit the electrical conductivity that is created by the presence of the dendrites. Solid electrolyte devices may thus have a two-state function: an “ON” state and an “OFF” state, and may perform the role of selector for example.
For exemplary purposes, FIG. 7 shows a simplified diagram of an electronic device 10 of the CBRAM type. This device 10 comprises a solid electrolyte 14, having for example a base of doped chalcogenide such as GeSe, arranged between a lower, nickel electrode 12, which serves as an inert cathode, and a portion of ionisable metal 16 having a silver base, that is to say a portion of a metal that readily forms metal ions (in this case silver ions Ag+), serving as the anode. An upper electrode 18 is arranged on the portion of ionisable metal 16. These elements are insulated electrically by lateral dielectric portions having an SiO2 or SiN base, arranged around these elements.
The state of a CBRAM memory device is produced by the difference in electrical resistivity between two states: ON and Off. In the OFF state, the metal ions (in this case Ag+ ions) yielded by the portion of ionisable metal 16 are dispersed throughout solid electrolyte 14. In this way, no electrical contact is made between the anode and the cathode, that is to say between the portion of ionisable metal 16 and lower electrode 12. Solid electrolyte 14 forms a highly resistive electrically insulating zone between anode 16 and cathode 12. A write operation in memory device 10 is performed by applying a potential difference between anode 16 and cathode 12. The Ag+ metal ions that are initially dispersed in solid electrolyte 14 then migrate towards cathode 12 to form a metal deposit. This metal deposit takes the form of metal nanofils, called “dendrites”, which grow progressively inside the electrolytic medium under the effect of the applied voltage and eventually creating bridges of electrical conductivity between anode 16 and cathode 12: this is the ON state. Solid electrolyte 14 then forms an electrically conductive zone due to the metal nanofils formed between anode 16 and cathode 12. A deletion operation is carried out by applying a potential difference with the opposite sign between electrodes 12 and 18, thereby causing the metal deposit (the nanofils) formed previously to “dissolve” into their ionic form in solid electrolyte 14, and enabling device 10 to return to the OFF state.
The use of a solid electrolyte type device as a series selector with the memory cell (instead of a p-n diode) also presents a number of difficulties. This mode of operation effectively requires controlled switching of the selector device that is independent of the read/write function of the memory cell. As a result, guiding the assembly is quite complex. Among other things, it necessitates switching of the selector to enable the resistive memory to be accessed or isolated.